倾斜排列差分过孔间串扰抑制方案Crosstalk suppression scheme between inclined differential vias
张慧超,王亚飞,李学华
摘要(Abstract):
针对高频下多层板上过孔间的串扰问题,提出了2种倾斜排列的差分过孔方案。所提方案在平行差分过孔排列方式的基础上将差分过孔偏移,通过倾斜排列来减小相邻差分信道间的耦合。在0.1~30 GHz的频域内对方案进行了仿真和分析。结果表明倾斜排列的差分过孔间串扰水平明显低于平行排列的差分过孔。相较于平行排列,在串扰抑制的最大点处,单对倾斜排列过孔的差分远端串扰和差分近端串扰分别降低了21.3 dB和6.9 dB,两对倾斜排列过孔差分远端串扰和差分近端串扰分别降低了10.5 dB和15.5 dB。
关键词(KeyWords): 串扰;差分过孔;倾斜排列
基金项目(Foundation):
作者(Author): 张慧超,王亚飞,李学华
DOI: 10.16508/j.cnki.11-5866/n.2024.01.002
参考文献(References):
- [1] RIMOLO-DONADIO R,GU A A,KWARK Y H,et al.Physics-based via and trace models for efficient link simulation on multilayer structures up to 40 GHz[J].IEEE Transactions on Microwave Theory and Techniques,2009,57(8):2072-2083.
- [2] LIM J,CHOW K S,ZHANG J,et al.ASIC package design optimization for 10 Gbps and above backplane serdes links[C]//2012 IEEE International Symposium on Electromagnetic Compatibility,Pittsburgh,PA,USA:IEEE,2012:199-204.
- [3] ZHANG M S.A High-density and low-crosstalk differential pin map for 112 Gb/s PAM4 applications[J].IEEE Microwave and Wireless Components Letters,2022,32(6):635-638.
- [4] FESHARAKI F,DJERAFI T,CHAKER M,et al.Mode-selective transmission line for chip-to-chip Terabit-per-second data transmission[J].IEEE Transactions on Components,Packaging and Manufacturing Technology,2018,8(7):1272-1280.
- [5] NICOLAESCU M,CROITORU V,TU■.Microstrip differential pair full wave electromagnetic analysis[C]//2022 14th International Conference on Communications (COMM),Bucharest,Romania:IEEE,2022:1-4.
- [6] WU S P,FAN J.Analytical prediction of crosstalk among vias in multilayer printed circuit boards[J].IEEE Transactions on Electromagnetic Compatibility,2012,54(2):413-420.
- [7] ZHANG Y J,FAN J,SELLI G,et al.Analytical evaluation of via-plate capacitance for multilayer printed circuit boards and packages[J].IEEE Transactions on Microwave Theory and Techniques,2008,56(9):2118-2128.
- [8] CHEN B C,PAN S M,WANG J D,et al.Differential crosstalk mitigation in the pin field area of SerDes channel with trace routing guidance[J].IEEE Transactions on Electromagnetic Compatibility,2019,61(4):1385-1394.
- [9] ZHOU P,SANG S H,HUANG Q Y,et al.Impact of anti-resonance caused by via structure on signal integrity in high-speed circuits[C]//2019 IEEE 3rd Advanced Information Management,Communicates,Electronic and Automation Control Conference (IMCEC),Chongqing,China:IEEE,2019:867-871.
- [10] SHIUE G H,YEH C L,LIU L S,et al.Influence and mitigation of longest differential via stubs on transmission waveform and eye diagram in a thick multilayered PCB[J].IEEE Transactions on Components,Packaging and Manufacturing Technology,2014,4(10):1657-1670.
- [11] WANG Y S,WANG H F,WU K.Undesired resonances in high-speed differential pair due to non-ideal return path design[C]//2019 IEEE International Symposium on Electromagnetic Compatibility,Signal & Power Integrity (EMC+SIPI),New Orleans,LA,USA:IEEE,2019:316-320.
- [12] 陈路.基于PCIe Gen4协议的高速串行链路信号完整性分析与优化设计技术研究[D].苏州:苏州大学,2019.CHEN L.Research on signal integrity analysis and optimization design of high speed serial link based on PCIe Gen4 protocol[D].Suzhou:Soochow University,2019.(in Chinese)